Computer systems and their processor architectures have various power savings states in order to provide an appropriate balance between power savings and performance. Many computer systems are compliant with the Advanced Configuration and Power Interface (ACPI) specification. In accordance with the ACPI specification, a processor may be operated in different power states identified as power states C0-Cn. Higher values for the index n correspond to deeper or “lower” power states, less activity, and, consequently, lower power consumption. Deeper power states, however, require longer transition times to place the processor back into the active execution state. In practice, deeper processor power states are characterized by higher interrupt latency because power saving is achieved by reducing the frequency of the clock and/or reducing the voltage. Voltage may be reduced to a retention level where state is preserved in the core or voltage may be reduced beyond the retention level. As state is lost, the latency to resume operation is increased. Further, the cache may also have its voltage reduced beyond retention levels. The deeper the power state is, the longer the exit latency in order to resume code execution.
In current computer systems, the north bridge represents a central decision node for transitioning the processor and dynamic random access memory (DRAM) into and out of low power states. In this context, the north bridge refers to those parts of a processor integrated circuit other than the processor cores. Thus, the north bridge may include functionality such as the memory controller and power management. Typically, power transitioning decisions are made by the north bridge, following operating system (OS) requests for specific processor power states. The depth of the processor power state is determined based on internal monitors and activity trackers in the north bridge.
Other components or circuits in a processor system, including input/output (I/O) servicing components such as the input-output hub, may also be controlled to operate in different power saving states or modes. For example, the power state of the processor component and the power state of the input-output hub could be managed independently.